Community Newsletter: June 2018

IN THIS ISSUE:

• Message from the Chair
  Highlights of 2018
• Join us at the 55th DAC
  Accellera breakfast, IP track panel, and more
• Accellera Events around the Globe in 2018
  Updates on worldwide standards events
• IP-XACT Working Group Update
  IP-XACT User Guide now available
• SystemC CCI 1.0
  New standard now available for download
• UVM
  UVM 2017 0.9 reference implementation now available
• Portable Stimulus Tutorial
  In-depth technical tutorial now available
• IEEE 1800-2017
  IEEE Standard Revision for SystemVerilog recently released

 

Message from the Chair

Accellera has been quite busy in the first half of 2018 with two DVCon events, the formation of a Proposed Working Group, and continued hard work on standards development.

DVCon U.S. and DVCon China both enjoyed great success earlier this year. DVCon China opened its second annual event to standing room only for the Portable Stimulus tutorial with attendees very engaged and enthusiastic. There was a great deal of activity in the exhibition as well, and many exhibitors expressed optimism about the business opportunities formed at the conference.

Earlier this year the Accellera Board of Directors approved the formation of a Proposed Working Group (PWG) to study the need for an IP Security Assurance Specification. The PWG held its first meeting in April with good attendance and a number of companies interested in pursuing the requirements for such a standard. We will keep you informed as things evolve with the PWG.

After almost three years of hard work and dedication, the Portable Stimulus Working Group is nearing completion of its release as an approved 1.0 standard. This is a significant milestone for Accellera, and we anticipate it will have a significant impact on the industry. The Board of Directors also just approved SystemC Configuration Control and Inspection 1.0 as an Accellera standard. This new and highly anticipated standard enables greater interoperability among tools and models and will greatly improve efficiency for model creators, system integrators and tool providers.

We value and encourage feedback from our members in our community forums and working groups. As we have new and emerging standards on the horizon, it’s important to have your voices heard and to get involved in the early stages of standards development.

I look forward to seeing you at DAC later this month and at our upcoming events such as SystemC Evolution Day, DVCon Europe and Accellera Day India this fall.

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

 

Join us at the 55th Design Automation Conference in San Francisco

Accellera Breakfast at DAC with Leadership Award and Technical Panel

Tuesday, June 26th
7:00-9:00 am
Moscone West, Room 3003

Accellera has been bustling this year with a lot of activity in current and emerging standards, and we have some exciting updates for you at DAC with Portable Stimulus nearing its 1.0 standard, the SystemC CCI Working Group just releasing its 1.0 standard, and the IP Security Assurance Proposed Working Group discussing standards development to address security of IP. We’ll have a panel with leaders from each of these groups presenting updates on their developments and activities, followed by questions from the attendees.

We invite you to join in the discussion following an update by Accellera Chair Lu Dai and the presentation of the Accellera Leadership Award. The Award is given to an individual who has provided active leadership and contributed significantly in the vision of EDA and IP standards development activities and the governance of Accellera Systems Initiative (and/or its precedent organizations).

The Accellera-sponsored breakfast is free to DAC attendees but registration is required.

A DAC IP Track Panel: Portable Stimulus Design & Verification (R)Evolution

Wednesday, June 27
1:30-3:00pm
Moscone Convention Center, Room 2008

The Accellera Portable Test and Stimulus Standard is the next inflection point in the IP verification and system-level validation productivity. Continuing the evolution of verification standards from SystemVerilog to UVM and now Portable Stimulus, verification engineers can now apply the proven techniques of constrained randomization and abstraction at the scenario level. The panel will explore the impact that the new Portable Test and Stimulus Standard will have on both design and verification IP, and the overall verification ecosystem.

Registration with the Design Automation Conference is required to attend this panel. Find out more about this panel.

IP Security Assurance Proposed Working Group Meeting at DAC

Wednesday, June 27
8:00-9:00am
Moscone West, Room 3005

Earlier this year the Accellera Board of Directors approved the formation of a Proposed Working Group (PWG) to investigate the need for an IP Security Assurance Specification. The kick-off meeting of the IP Security Assurance PWG was held in April with more than 50 participants. The PWG is open to all interested parties for a period of six months after its inception. For more information about the PWG, visit here. This meeting is open to all interested parties.

 

Accellera Events around the Globe in 2018

DVCon U.S.

DVCon U.S. concluded its 30th annual technical conference and exhibition with more than 1,000 attendees and exhibitors participating in the four-day event.

“We continually strive to improve the conference each year to give practicing design and verification engineers the latest and most valuable information on current and emerging standards under one roof over four days,” stated Dennis Brophy, DVCon U.S. 2018 General Chair. “We have grown to keep pace with the needs of our returning and new attendees and added short workshops and some new topic areas this year such as automotive security and RISC-V that were very well-received. In addition to the technical program, the Expo continues to bring people together to discuss the latest technologies and issues they face with exhibitors and their peers. The floor was full each afternoon and the conversations were lively.”

DVCon U.S. 2019 will be held February 25-28, 2019 at the DoubleTree Hotel in San Jose, California, with Aparna Dey as General Chair. The 2019 Call for Papers will be available on June 14, 2018.

DVCon China

DVCon China concluded its second annual conference in Shanghai in April to increased attendance and standing room only tutorials. The Portable Stimulus and UVM tutorials and keynotes were very well-received. Short workshops were added to the program this year and sponsorship of all four of them filled up quickly. The exhibition was very busy with a lot of activity at each booth as attendees interacted with the vendors to learn more about their products and solutions.

SystemC Evolution Day

The third SystemC Evolution Day will be co-located this year with DVCon Europe 2018 and will be held at the Holiday Inn in Munich, Germany on Tuesday, October 23, 2018. DVCon Europe will open the following day. The full day technical workshop on the evolution of SystemC standards will have several in-depth sessions focused on current and future standardization efforts regarding SystemC. It is a user-centric, hands-on workshop that brings together experts from the SystemC user community and the Accellera working groups to advance SystemC standards.

The organization team is led by Philipp A. Hartmann (Intel), Oliver Bell (Intel), Martin Barnasconi (NXP), Joachim Geishauser (NXP), Matthias Bauer (Infineon), Volkan Esen, (Infineon) and Andrew Stevens (Infineon). This event is free but registration is required to attend and space is limited. More information about SystemC Evolution Day can be found here. The Call for Contributions deadline is June 30.

Presentations and information about the 2017 workshop are available here.

DVCon Europe

DVCon Europe 2018 will be held at the Holiday Inn in Munich, Germany, on October 24 and 25.

“I am very pleased to see that DVCon Europe has become a well-established technical conference since its inception in Europe five years ago,” stated Martin Barnasconi, DVCon Europe General Chair. “DVCon Europe is clearly recognized by the design and verification community as a highly technical conference and exhibition focused on practical application, made for engineers by engineers.” Technical experts from around the world will come together to share the latest developments and experiences on the application of EDA languages, methodologies and tools for the design and verification of electronic systems and integrated circuits.”

To view the proceedings from DVCon Europe 2017, visit here. Registration will open in August and the program will be available in early August. To read the DVCon Europe Blog, visit here.

Accellera Day India 2018

Accellera Day India will be an in-depth full day technical program held in Bangalore, India in late fall 2018. It will have a similar format to Accellera Day at DVCon U.S. with a morning tutorial, a luncheon with a keynote speaker, and an afternoon tutorial. More information will be available soon. Stay tuned!

 

IP-XACT Working Group Update with Erwin de Kock

The IP-XACT standard describes the metadata of IP designs and flows and the interconnection of IP interfaces in a standard specification. It defines a standard way to describe key details about an IP, such that users of the IP, both people and tools, can access the information in a consistent and potentially automated fashion. To give designers a better understanding of this important standard and how to use it, the IP-XACT Working Group has worked diligently to provide information on user perspectives supported by meaningful data. The IP-XACT User Guide is now available for download, and our hope is that it will help designers understand the different parts of the standard and how they are related.

With the User Guide complete, our working group held a face-to-face meeting in April in Eindhoven to discuss our next steps and to begin development of a revision to the IEEE 1685 standard. We developed a list of new requirements that we have since frozen as we focus on developing the next version of IP-XACT. The working group will have discussions bi-weekly to continue to further refine the new list, adding more detail and proposed implementations. We’ll meet face-to-face again toward the end of the year to close on the remaining requirements and proposed solutions.

We welcome participation from all Accellera members to help us as we fine-tune the new version. We encourage you to engage in our forum discussions to provide feedback and to help give you the information you need to take advantage of the benefits IP-XACT has to offer.

 

New SystemC Standard Available!
Accellera Announces SystemC Configuration, Control & Inspection (CCI) 1.0

The Accellera Board of Directors recently approved SystemC CCI as a 1.0 standard. The SystemC Configuration standard is important because it will allow utilization of any compliant tool’s configuration capabilities with any model using a compliant configuration library. It has been architected to allow existing model configuration solutions to achieve compliance through a bridge, avoiding the necessity to update models and streamlining migration. For more information on SystemC CCI 1.0, read the press release or visit the working group page. Download SystemC CCI 1.0 here.

 

New UVM Reference Implementation Now Available

The Accellera UVM Working Group has released the UVM 2017 0.9 reference implementation. This implementation is available as a SystemVerilog class library and is fully compatible with the IEEE 1800.2-2017 standard as defined in the Language Reference Manual. The library can be downloaded for free here. The IEEE 1800.2-2017 standard is available free of charge from the IEEE Get program, courtesy of Accellera. We encourage you to visit the UVM forum to provide feedback, ask questions, and engage in discussions.

 

Portable Stimulus Tutorial Now Available

The DVCon U.S. 2018 tutorial "Portable Test and Stimulus: The Next Level of Verification Productivity is Here" is now available online (registration is required). This in-depth technical tutorial focuses on a set of typical design use cases from a variety of applications and shows how to use the upcoming Portable Stimulus Standard to create an abstract model of your verification intent. The tutorial then demonstrates how these models can be used to generate scenarios to be executed on the different platforms and environments used in your development process, and how the models can be reused and leveraged from project to project. A Q&A session with the Portable Stimulus Working Group follows the tutorial.

For more information about the Portable Stimulus Working Group, visit the working group page where you will find links to the latest information, community page, and forum discussions.

 

Recently Released: IEEE Standard Revision for SystemVerilog

IEEE recently published the standard revision IEEE 1800: SystemVerilog – Unified Hardware Design, Specification and Verification Language. The revision to IEEE 1800 addresses feedback from standard users working with complex integrated circuits to address inconsistencies and correct discovered errata. IEEE 1800-2017 is available for download at no cost through the Accellera-sponsored IEEE Get Program. For more information, read the IEEE press release.

 

 

2018 Global Sponsors

Are you interested in becoming a Global Sponsor? Find out more about our Sponsorship Package.

 

Copyright 2018 Accellera Systems Initiative