Accellera at Virtual DAC 2020

Accellera’s Functional Safety Working Group Addresses Standardization Efforts to Improve Automation, Interoperability, and Traceability

Thursday, July 23
Noon-1:00pm

We invite you to join us for our virtual lunch break at DAC focused on Functional Safety. The mission of our recently formed Functional Safety Working Group (FSWG) is to develop a standard to provide a comprehensive and unified definition of the Functional Safety intent to improve automation, interoperability, and traceability across the Functional Safety development lifecycle of electronic circuits and systems.

Join us as we present an overview of the scope, needs, and goals defined by the FSWG including developments since its formation. Introductions by Lu Dai, Accellera’s Chair, Martin Barnasconi, Technical Committee Chair, and Alessandra Nardi, FSWG Chair, are followed by several informative presentations by functional safety experts focusing on specific perspectives, challenges, and opportunities. You have an opportunity at the end of the presentations to ask questions of the participants during a live Q&A session. Speakers include Bala Chavali, RAS Architect - Principal Member of Technical Staff, AMD; Ghani Kanawati, Technical Director of Functional Safety, Arm; Jyotika Athavale, Principal Engineer and Lead Platform Technologist, Intel; Franck Galtié, Director Automotive Functional Safety, NXP Semiconductors; and Riccardo Vincelli, Director of Functional Safety Competence Center, Renesas.

For the link to the session on the DAC website, visit here.

The lunch break panel is free, but registration through DAC is required to attend. You can register for “I Love DAC” with no fees.

Why Care About IP Security Assurance – What Could Go Wrong?

Tuesday, July 21
1:30-3:00pm

Organized by IPSA Working Group Chair Brent Sherman, this IP Track Session will discuss Accellera’s emerging IP Security Assurance standard aimed at addressing security concerns in IP. It will also provide a discussion on 3rd-party IP security risks associated with FPGA bitstream integration and key learnings from an IP supplier performing security assurance.

Registration with the Design Automation Conference is required to attend this presentation. Find out more about this session here.

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