Join Us for Accellera Day at DVCon U.S. 2020

Monday, March 2
Design & Verification Conference and Exhibition
DoubleTree Hotel, San Jose, CA

Accellera invites you to join us as we open DVCon U.S. with a day focused on standards development and technologies that you can apply immediately and those that will help to shape future activity.

Agenda

9:00am-12:00pm — Tutorial: Portable Stimulus: What's Coming in 1.1 and What it Means For You

12:00pm-1:30pm — Accellera Sponsored Luncheon

1:45pm-3:15pm — Short Workshop: An Introduction to the Emerging IP Security Assurance Standard

3:30pm-5:00pm — Short Workshop: How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity

5:00pm -7:00pm — DVCon Expo and Reception

6:30pm – 7:30pm — Functional Safety Working Group Birds of a Feather

Registration is now closed.

Tutorial: Portable Stimulus: What's Coming in 1.1 and What it Means For You

With the release of the Portable Test and Stimulus Standard (PSS) 1.0 in June 2018 (with 1.0a following in January 2019), users have begun to take advantage of this exciting new technology to create abstract models of verification intent that can be used to generate target-specific implementations on a variety of platforms, including simulation, emulation, and virtual and FPGA prototypes. Since that time, the Accellera Portable Stimulus Working Group (PSWG) has continued to work on adding additional requirements to the Standard to expand the modeling capabilities, and to maximize the reusability of portable stimulus descriptions.

This 3-hour technical tutorial, presented by several contributing members of the PSWG, will provide attendees with an overview of the proposed PSS 1.1 standard. We will review the basic modeling constructs, use model and test realization specifications in a PSS verification intent model and show the enhanced capabilities being implemented for 1.1.

Speakers:
Tom Fitzpatrick - Mentor, A Siemens Business
Matan Vax - Cadence Design Systems, Inc.
Prabhat Gupta - Advanced Micro Devices, Inc.
Hillel Miller - Synopsys, Inc.
Karthick Gururaj - Vayavya Labs Pvt., Ltd.

Organizer:
Tom Fitzpatrick - Mentor, A Siemens Business

Accellera Luncheon

We hope you’ll join us for our annual Accellera Day Luncheon where Chair, Lu Dai, will provide an update on Accellera activities followed by the presentation of the 2020 Technical Excellence Award. Alessandra Nardi, Chair of the Functional Safety Working Group will introduce the charter of our newest WG. In addition, as a follow-up to the in-depth technical discussion during the morning tutorial on the Portable Stimulus Standard (PSS), we will have a panel that will provide attendees the opportunity to interact with members of the Portable Stimulus Working Group and ask their most pressing questions. If you’d like to ask about additional details regarding specific features of PSS or about plans for the standard and anticipated industry reaction, you won’t want to miss this panel discussion.

All of Monday’s attendees are invited to this Accellera-sponsored luncheon.

Short Workshop: An Introduction to the Emerging IP Security Assurance Standard

A System on Chip (SoC) or Application Specific Integrated Circuit (ASIC) is comprised of multiple components referred to as Intellectual Property (IP) blocks or just IP. These blocks come from multiple sources such as internal development teams, IP suppliers, tool-generated IP, etc. Typically, the SoC/ASIC owner integrates multiple IPs from multiple sources, which raises concerns about the security risk. How much risk is the Silicon owner (i.e., Integrator) inheriting? What potential security concerns exist that the Integrator must address to ensure the security objectives of the SoC/ASIC are upheld? The workshop will introduce an emerging new standard called IP Security Assurance (IPSA) to address these concerns in a manner that is low-overhead, non-disruptive, and scalable across IP families. The standard specifies an approach to highlight IP assets and associated known security weakness entries in a knowledge base for the mitigation implementer to address.

The workshop will focus on the following which is based on the whitepaper:

Methodology which details the overall concept and workflow along with the individual components, dependencies, and assumptions.
Security weakness knowledge base that highlights potential IP security concerns.
OpenCores examples to demonstrate how the methodology applies to real IP cores.
Summary and Outlook which details the road map and expectations moving forward. This includes integrator's obligations when integrating IPSA-ready IP and suppliers' obligations to sustaining assurance with IPSA-ready IP.

Speakers:
Brent Sherman - Intel Corp.
Ambar Sarkar - NVIDIA Corp.
Adam Sherer - Cadence Design Systems, Inc.
Mike Borza - Synopsys, Inc.

Organizer:
Brent Sherman - Intel Corp.

Short Workshop: How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity

HLS has long promised that it could deliver dramatic productivity by raising the level of abstraction but there have always been questions regarding the fit of this technology and the results that it could achieve vs hand-coded RTL and what an overall HLS design and verification methodology would look like.

This 90-minute tutorial will begin with an introduction to the SystemC Synthesizable Subset and an introduction to basic concepts of how HLS works to go from SystemC/C++ description to quality RTL. It will then leave a majority of the time for the audience to hear from two leading semi-conductor vendors about real-world use-cases and the results they have achieved; Intel and NVIDIA.

Matt Bone of Intel will describe their challenges and successful techniques for design space exploration and tuning of algorithmic and fabric-oriented designs.

Rangharajan Venkatesan of NVIDIA will describe their open-source HLS library, MatchLib, and present a case study for fast prototyping of a Machine Learning accelerator using object-oriented HLS methodology.

Speakers:
Mike Meredith - Cadence Design Systems, Inc.
Stuart Swan - Mentor, A Siemens Business
Matt Bone - Intel Corp.
Rangharajan Venkatesan - NVIDIA Corp.

Organizer:
Ellie Burns-Brookens - Mentor, A Siemens Business

DVCon Expo & Reception

A DVCon reception is a chance for conference attendees to network at the end of the each day. Come and enjoy cocktails and conversations in a casual environment with the DVCon Exhibitors. Mingle from booth to booth while enjoying food and drinks.

Functional Safety Working Group Birds of a Feather

The Functional Safety Working Group (FSWG) will be holding a Birds of a Feather at DVCon U.S. on Monday, March 2 from 6:30-7:30pm in the San Jose Room at the DoubleTree Hotel. During this session, the ongoing activities of the FSWG will be discussed, along with a Q&A with the attendees interested in joining this standardization initiative.