Community Newsletter: November 2021


IN THIS ISSUE:

 

Message from the Chair

Lu Dai, Accellera Systems Initiative ChairIt is hard to imagine 2022 is just around the corner. We still have a lot to look forward to before the end of the year. The Design Automation Conference in San Francisco will be one of the first gatherings of our industry in nearly 18 months. Accellera will be hosting a luncheon Town Hall focused on Functional Safety, and members of our IP Security Assurance Working Group will be presenting a tutorial on the new SA-EDI 1.0 standard. We hope you will join us.

Please also keep a look out for news from our working groups. The UVM-AMS Working Group will have a whitepaper available in the coming months, and the SystemC Verification Working Group is preparing the next release of the UVM-SystemC Reference Implementation including a draft standard. The SystemC Language Working Group has incorporated community feedback in the publicly available SystemC Reference Implementation as part of the preparation of the next release of the SystemC class library. Stay tuned for more information on these exciting developments!

DVCon India 2021 and DVCon U.S. 2022 will be held virtually; DVCon Europe and SystemC Evolution Day recently concluded their virtual events to much success. Read more about the Accellera-sponsored events in the newsletter below.

We look forward to interacting with you in the coming year and hope to see you at our conferences virtually or in-person. As always, please stay in touch via our community forums, or if you are not already an Accellera member and are interested in joining for the new year, please get in touch.

With 2021 almost in the rearview mirror, Accellera wishes you all a safe and happy holiday season and a healthy new year.

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

 

Q&A on systemc.org

SystemC

Q&A with Accellera Technical Committee Chair Martin Barnasconi on the New SystemC Community Portal

Q: What are the goals for new systemc.org website?
A: systemc.org is the new SystemC Community Portal, with online references to everything related to SystemC. The ambition is to make systemc.org the entry portal for everyone who is looking for relevant and up-to-date SystemC information.

Q: What inspired Accellera to revive systemc.org?
A: The organization committee of the SystemC Evolution Day as well as the chairs of the Accellera SystemC Working Group felt the need to bring SystemC knowledge together in one central location.

The SystemC ecosystem is very rich and diverse, but information is also a bit scattered, and people who like to learn more about SystemC might have difficulties finding all of the information. The new SystemC Community Portal is a focal point to help people find their way in the broad SystemC ecosystem.

Q: How does the community provide updates?
A: The actual content of the website is hosted on GitHub in the publicly accessible repository accellera-official/systemc.org. Everyone can submit changes or additions in the form of pull requests. In this way, the community itself can keep the portal vibrant and up to date.

Q: How could this be a resource for the academic community?
A: Many universities and research institutes around the world are teaching and using SystemC, and references to university courses and curriculums will be added to systemc.org soon.

In this way, the ambition is to grow the academic network of universities and organizations interested in making SystemC an integral part of their educational program.

Q: Who maintains systemc.org?
A: The systemc.org domain and source repository at accellera-official/systemc.org are managed by Accellera Systems Initiative. The SystemC Working Groups in Accellera are responsible for the evolution of the SystemC language standard and associated libraries. The technical experts in these working groups also act as moderators for the content available at systemc.org.

 

Join us at the 58th Design Automation Conference

DAC 2021Accellera Town Hall Focused on Functional Safety Led by a Panel of Industry Experts – Join us for Lunch and a Lively Discussion!

Monday, December 6
11:45am – 1:15pm PST
Room 3001

Register Now

Topic: Where is the Functional Safety Standard and Why Adopt It?

We invite you to join us for a town hall lunch at DAC focused on Functional Safety. The mission of our Functional Safety Working Group (FSWG) is to develop a standard to provide a comprehensive and unified definition of the Functional Safety intent to improve automation, interoperability, and traceability across the Functional Safety development lifecycle of electronic circuits and systems.

Functional safety is a growing cornerstone of modern designs. Automotive, avionics, medical, industrial automation, and other market segments have developed rigid and structured processes and techniques to support safety-critical design. Yet many challenges are still being addressed:

  • Is safety really different from any other design and verification metric?
  • What are the costs involved?
  • Is safety compliance a real value?
  • How can we ensure devices operate as they should and are safe throughout their lifecycle?
  • Can designs meant for one segment be leveraged in another?
  • What is the connection to security?

Join us for lunch as our group of experts discuss their perspectives on the issues, as well as the exciting future of functional safety. Members of the Accellera Functional Safety Working Group will provide insight into the mission of the working group and progress toward development of its emerging standard. Attendees will have an opportunity to ask questions, so come prepared for what is sure to be a thought-provoking discussion.

Facilitator for Town Hall Discussion: Alessandra Nardi, Accellera Functional Safety Working Group Chair

Town Hall Participants:

  • Alex Palus, AMD
  • Ghani Kanawati, Arm
  • Bharat Rajaram, Texas Instruments
  • Serge Leef, DARPA

The Accellera-sponsored luncheon is free to DAC attendees, but registration is required.

Presentation: “Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology”

Wednesday, December 8
1:30pm - 3:00pm PST
Designer, IP and Embedded Systems Track Presentation

There has been an exponential growth in hardware vulnerabilities over the last few years. These exploits are becoming more widespread, dangerous, and costly than ever and are coming from multiple attack vectors. With many being remotely exploitable, such the widely publicized Spectre and Meltdown attacks, the impact of an attack can be enormous.

This tutorial will address these concerns and will include an introduction to Accellera’s Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0.

Registration with the Design Automation Conference is required to attend this presentation. Find out more about this session here.

 

Accellera Events around the Globe

DVCon India 2021

DVCon India 2021The sixth edition of DVCon India will be held December 14-16 on a virtual platform.

The three-day program opens with a Vision Talk presented by Anil Kempanna, Vice President of IOTG, Intel, followed by a keynote given by Ashok Chandran, Fellow, Analog Devices.

Day One will also have a tutorial from Accellera’s UVM-AMS Working Group titled “UVM for Mixed-Signal Verification.” Members will present their findings, requirements, and ideas collected so far, as well as the next steps for developing the proposed standard. Accellera’s Functional Safety Working Group will also present an update on the current efforts of the working group.

Registration opens soon. To view the complete advance program, visit here. For additional information about DVCon India 2021, visit the website.

DVCon U.S. 2022 – Registration is Open!

DVCon U.S. 2022The 34th annual DVCon U.S. 2022 will be held on a virtual platform February 28 – March 3, 2022. The steering committee has been hard at work putting together an outstanding technical program that will include a keynote, tutorials, papers, posters, panels, short workshops, and a virtual exhibition.

Registration is open and the program will be available December 3. Please check the website for the most up-to-date information.

DVCon China 2022 – Call for Abstracts is Now Open

DVCon China 2022Join us for DVCon China 2022 on April 27th at the Renaissance Pudong Hotel in Shanghai. The Call for Abstracts is now open and the deadline to submit your proposals is December 18, 2021. More information on workshop and tutorial proposals will be posted soon. Please check the website for ongoing updates.

Upcoming Accellera Events in 2022

For more information on upcoming events throughout the year, please visit the Accellera Events Page. Information on each event will be updated as soon as it becomes available.

 

Post-Event Summaries

DVCon Europe 2021 – Record Attendance!

DVCon Europe 2021DVCon Europe concluded its eighth conference and exhibition with a record 465 attendees coming to the virtual platform from 24 countries and 149 different organizations. There were four keynotes, two panel sessions, 13 tutorials, 24 paper presentations, and 13 poster presentations.

The conference featured a full virtual reality 3D world, modeled on a conference center in Munich and incorporating a stage for the keynotes as well as rooms for the poster sessions.

The award for Best Paper went to Ana Sanz Carretero, Katherine Garden and Wei Cheong from Xilinx for their paper, “Testbench Flexibility as a Foundation for Success.”

Honors for Best Poster were awarded to Caglayan Yalcin and Aileen McCabe of Qualcomm for their paper, “An Analysis of Stimulus Techniques for Efficient Functional Coverage Closure.”

“We are proud to have achieved a record high number of registrations and, since networking is an important part of DVCon Europe, we are very happy that we’ve been able to continue to offer these opportunities over the last two years,” commented Sumit Jha, General Chair of DVCon Europe 2021.

For those that registered, the virtual platform will be open through November 26. For more information on DVCon Europe, visit here.

Save the date! DVCon Europe 2022 will held December 6-7 in Munich, Germany.

SystemC Evolution Day 2021

SystemC Evolution Day 2021The sixth SystemC Evolution Day took place on October 28th, 2021. We had presentations and discussions on technical topics, such as fork/join of threads, multi-core debugger integration, and formal verification. We also had the yearly update from the SystemC-related working groups in Accellera and a presentation about using SystemC in hybrid simulations, where simulations representing different standards/technologies shall be combined – a challenge both from a technological and organizational perspective.

The SystemC community is vibrant, and it now has access to visit and contribute to the newly (re-)opened systemc.org website. A presentation about this valuable resource was given at SystemC Evolution Day, followed by discussions around publicly available material and its relation to the actual standardization work in the Accellera working groups.

We mingled in the virtual environment, generously shared to us by the DVCon Europe team, and we had discussions (as avatars, but with sound as well as vision) around current and future technological (but also community-related) SystemC topics.

We had approximately 65 unique visitors throughout the day, representing users as well as tools and services providers. We concluded the day with a summary of our impressions, observing that we had ideas for standardization updates as well as interesting topics to pursue. Technical areas such as multi-simulator scenarios and community-related topics such as the systemc.org website are just a couple of the exciting items of interest moving forward.

We look forward to your participation in one of our next SystemC events!

Sincerely,
Ola Dahl, SystemC Evolution Day Chair

For more information on SystemC Evolution Day, including past presentations, visit here.
For more information on SystemC Evolution Fikas visit here.

Save the date! SystemC Evolution Day 2022 will be held following DVCon Europe on December 8, 2022.

 

IEEE Get Program Update

Since its inception, the Accellera-sponsored IEEE Get Program has resulted in more than 134,831 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEEE Standards page on the Accellera website.

 

 

Accellera Global Sponsors

CadenceSiemens EDASynopsys

Contact us if you interested in becoming a Global Sponsor.

 

Copyright 2021 Accellera Systems Initiative