Community Newsletter: February 2017

IN THIS ISSUE:

Message from the Chair
An introduction by new Chair Lu Dai
Accellera Events around the Globe in 2017
Mark your calendars for exciting events in 2017
Working Group Spotlight
New UVM co-Chairs and latest developments
Portable Stimulus Webinar Update
Series rescheduled to incorporate recent advancements

Message from the Chair

Lu Dai, Accellera Systems Initiative Chair

As the newly elected Chair of the Accellera Board of Directors, I'd like to introduce myself to our community.

I started my engineering career at Intel and then became a design verification lead at Cisco, during which time I evaluated many design and verification tools personally. As a result I became the first user of quite a few successful startup tools. After moving to Qualcomm in sunny San Diego, I led the design verification of multiple generations of Snapdragon SOCs. I am currently leading front-end design and verification initiatives, ensuring that consistent flow and methodologies are applied across Qualcomm.

As the new Chair, I want to reaffirm our commitment to open standards and interoperability. 2017 will witness the release of SCE-MI 2.4 and a new standard for Portable Test and Stimulus as well as UVM-SystemC, SystemC CCI, and SystemRDL 2.0. We will also have our first ever DVCon in China, extending our reach into this important new user community. Our online community site recently introduced the addition of IP-XACT. This is in addition to our OCP, SystemC, and UVM communities that have already established a loyal following. We encourage you to give this excellent resource a try and to provide feedback so that we could make it an even better destination site for standards development and learning.

I'd also like to take this opportunity to thank Shishpal Rawat and Yatin Trivedi for their contributions to Accellera over the years. Both have served on the Board of Directors as Officers for many years. I also want to thank the Board for their trust in me. I want to assure our community about our commitment to continue Accellera's tradition in being the leader in developing open standards. I highly encourage you to join us at DVCon U.S. in San Jose, CA, for which we have a packed agenda of excellent papers, panels, and tutorials. I am looking forward to meeting you there and to working with you in moving Accellera forward.

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

Accellera Events around the Globe in 2017

DVCon U.S.

In just two weeks DVCon U.S. will be in full swing in San Jose, California. In its 29th year, DVCon U.S. continues to be the must-attend conference for design and verification engineers and those in the EDA industry focused on tool development and the application of standards.

Accellera Day kicks off the conference on Monday, February 27 with a tutorial dedicated to the emerging Portable Stimulus Standard (PSS), "Creating Portable Stimulus Models with the Upcoming Accellera Standard." The first version of the Accellera PSS is nearing completion. This timely tutorial presents an introduction to the standard's main features leveraging a series of usage examples defined by working group members that represent many of the common challenges faced in today's multi-core designs.

The PSS tutorial will be followed by an Accellera-sponsored luncheon with an Accellera update provided by our new Chair, Lu Dai; the presentation of the Accellera Technical Excellence Award; and a Town Hall Discussion that will provide an opportunity for questions from the morning tutorial as well as updates on SystemC activities and future directions for the UVM Working Group.

Monday afternoon will have two tutorials: "Introducing IEEE 1800.2 – The Next Step for UVM," and "SystemC Design and Verification – Solidifying the Abstraction above RTL."

The conference's keynote, "Tomorrow's Verification Today," will be delivered Tuesday by Anirudh Devgan, Senior Vice President and General Manager of the Digital & Signoff Group and System & Verification Group at Cadence. He will review the latest trends that are redefining verification from IP to system-level, with an increasingly application-specific set of demands changing the landscape for hardware and software development.

There are numerous paper and poster sessions to choose from on Tuesday and Wednesday as well as two intriguing panels on Wednesday: "Users Talk Back on Portable Stimulus," and "SystemVerilog Jinxed Half My Career: Where Do We Go from Here?" There will also be plenty of networking opportunities throughout the four-day conference and exhibition. The expo will be held Monday through Wednesday with a booth crawl Monday evening and receptions Tuesday and Wednesday evenings. There are six sponsored tutorials to choose from on Thursday on a wide range of design and verification topics and challenges.

DVCon will also host a special session presented by Harry Foster titled, "Trends in Functional Verification: A 2016 Industry Study" based on the Wilson Research Group's 2016 study. The findings from the 2016 study provide invaluable insight into the state of today's electronics industry.

If you haven't already, register today for DVCon U.S.! You won't want to miss this exciting, comprehensive program and exhibition. It's an opportunity to gather in one place to meet with members of the design and verification community to share ideas, discuss challenges, and learn about technology that is applicable in your day-to-day job today.

DVCon China

The first DVCon China will be held April 19, 2017 in Shanghai. There will be two keynotes during the conference: Yong Fu, Senior Director of CAE at Synopsys, will provide the keynote "What's Next in Verification?" and Wally Rhines, President and CEO of Mentor Graphics, will provide the keynote "Design Verification: Challenging Yesterday, Today and Tomorrow."

DVCon China attendees will have the opportunity to take part in the many informal, but often intense, technical discussions that pop up around the conference venue among 200+ design and verification engineers and engineering managers. China has seen vast improvements in the IC industry in recent years, and DVCon China will help continue this growth by bringing an international perspective to China. This networking opportunity among peers and university students is an invaluable benefit to DVCon attendees. Finally, DVCon China attendees have access to the vendors of advanced design and verification tools, IP/VIP, and services who exhibit at the conference.

Registration is open. Advance registration is available through March 17.

Accellera Verification and System-Level Design Forum Taiwan

The 2016 movie "Passengers" portrays a future of space travel. Sleeping in a dormant state for 120 years, the crew and passengers journey through the universe relying on a spacecraft entirely controlled by artificial intelligence. One can barely imagine the scale of effort in design and verification that would need to be conducted before such machines could ever be trusted by humans. Obviously today we see only the slim light of dawn of the massive applications of AI. We are already getting a glimpse into the near future with the Tesla autopilot vehicles and the AlphaGo’s winning streaks over human masters. As such, the Accellera Verification and System-Level Design Forum looks into technologies flourishing in the past five years that push the success of multiple-core SoC and are now pushing the progress of the IoT, fog computing, and edge computing. The forum covers the latest topics and methodologies in verification, system-level design, and portable stimulus developed and standardized by Accellera.

This one-day event will be held April 21, 2017 in Hsinchu, Taiwan at the Ambassador Hotel.

More information will be announced soon — check our events page for upcoming details.

DVCon India

Mark your calendars! DVCon India will be held September 14-15, 2017 at the Leela Palace in Bangalore, India.

The Call for Abstracts will be open for submissions from March 1 through April 25, 2017.

DVCon Europe

Save the date! DVCon Europe will be held October 16-17, 2017 in Munich, Germany.

The Call for Papers will be open for submissions from March 9 through April 4, 2017.

Working Group Spotlight – UVM

UVM The UVM (Universal Verification Methodology) Working Group recently elected Justin Refice, NVIDIA, and Mark Strickland, Cisco, as co-Chairs of the working group. With the recent submission of UVM 1.2 as a contribution to the IEEE P1800.2™ Working Group for further standardization and maintenance, the Accellera UVM Working Group is responsible for developing the Library Reference Implementation for the IEEE P1800.2 UVM base class API standard.

The next step for the group is to determine its new set of priorities and how they will be accomplished. They will also be working to define backwards-compatibility constraints, define a flow for resolving open Mantis issues, and define a reference implementation release schedule. After the first release of IEEE 1800.2, the working group will determine ways to help UVM 1.2 users transition to use the IEEE 1800.2 API.

To find out more about UVM, attend the Accellera tutorial at DVCon U.S. 2017, "Introducing IEEE P1800.2 – The Next Step for UVM" on Monday, February 27 at 2:00pm.

Portable Stimulus Webinar Update

With the emerging Portable Stimulus Accellera standard making significant progress, the webinar has been rescheduled for spring 2017 to enable us to showcase and discuss the latest developments. Details will follow after DVCon U.S. 2017.

2017 Global Sponsors

Are you interested in becoming a Global Sponsor? Find out more about our Sponsorship Package.