Tutorial: Creating Portable Stimulus Models with the Upcoming Accellera Standard

Presented at DVCon U.S. 2020 on February 17, 2020

Portability of reusable test cases has long been a goal for semiconductor verification and validation teams. No one wants to “reinvent the wheel” by having to rewrite similar tests again and again. While the widely accepted, Accellera Universal Verification Methodology (UVM) standard, enabled reuse of testbench components and constrained-random tests at the IP and block level, limitations in terms of reuse at subsystem and full-chip level, and lack of portability across execution platforms required a fresh look at addressing the portable stimulus and test challenge. Accellera Systems Initiative formed the Portable Stimulus Working Group (PSWG) in early 2015 to do just that. The group’s charter is to define a portable test and stimulus standard specification to permit the creation of a single representation/model, usable by a variety of users across different levels of integration under different configurations, enabling the generation of different implementations that run on a variety of execution platforms, including, but not limited to, simulation, emulation, FPGA prototyping, and post-silicon. With such a specification in place, EDA vendors can produce tools that automatically generate stimulus, results checks, and coverage metrics tuned for a particular target.

The first version of the Accellera Portable Test and Stimulus Standard (PSS) is nearing completion. This timely tutorial presents an introduction to the standard’s main features leveraging a series of usage examples defined by PSWG members that represent many of the common challenges faced in today’s multi-core designs. The tutorial will show with actual coding examples how the verification and portability challenges of these examples are met using the standard.

Viewers will learn how to:

• Understand and develop abstract, portable test and stimulus models for their chip designs
• Use PSS constraints to guide randomization of both data and control flow to describe a legal scenario space to be verified
• Target use of existing low-level sequences or drivers in the generation of tests
• Execute generated tests across platforms from simulation, emulation, FPGA prototype, and post-silicon to verify a complete chip or multi-chip system
• Specify and gather coverage metrics at every step to assess verification completeness

The tutorial is split into three parts:

• Part 1: Portable Stimulus: The Next Leap in Verification & Validation Productivity and Introducing Portable Stimulus Concepts & Constructs
  Faris Khundakjie, Intel and Tom Fitzpatrick, Mentor; Contributions by David Brownell, Analog Devices
  (00:00)
  
  
• Part 2: Building System-Level Scenarios and Generating Tests from Portable Stimulus
  Sharon Rosenberg, Cadence and Adnan Hamid, Breker Verification Systems
  (53:14)
  
  
• Part 3: Coverage in Portable Stimulus, The Hardware/Software Interface Library, and What’s Next for Portable Stimulus
  Srivatsa Vasudevan, Synopsys; Karthick Gururaj and Sandeep Pendharkar, Vayavya; Faris Khundakjie, Intel
  (1:33:06)
  
  

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