Tutorial: Automating Design and Verification of Embedded Systems Using Metamodeling and Code Generation Techniques
Presented at DVCon U.S. 2015 on March 2, 2015
This tutorial presents the application of the known SW development methodology “Metamodeling and Code Generation” to the design of SOCs, mainly the semi-automated generation of SystemC prototypes, firmware and hardware (RTL, schematic) as well as verification measures such as elements of a SystemVerilog UVM testbench or SVA properties for those. It also covers the IP-XACT and UML standards that are widely used in ESL design.
Metamodeling opens a complete new modeling space for hardware designers. Instead of thinking in models-of-computation or description languages, the designers think and model in terms of things, attributes of these things, and their relationships. The description of involved things, attributes, and relationships is described in a so called Metamodel. A Model, being an instance of a Metamodel describes one specific thing with its sub-elements, attribute values, and relation settings.
AIn addition, parts of existing Metamodel definitions from UML, SysML, or IP-XACT can be used to define the structure of the models. Often parts of the model can be extracted from specification, thus improving consistency in the design process. After having built a model, code can be generated from that model. This can be done via handcoded generators or template engines.
The tutorial (a detailed structure available on request) starts with the introduction of Metamodeling concepts and techniques and shows that Metamodeling already has over 20 years of history in hardware design. Following that is the presentation of standard Metamodels in the hardware domain and the discussion of their application. The tutorial ends with a set of application examples, each of which can be directly utilized by attendees since they are based on open-source Eclipse and XML technologies.
The tutorial is prepared and given by design, verification, as well as (meta-) modeling experts, which work for globally known companies, research institutes, and universities. This mix ensures a depth of engineering content and breadth of real-life examples.
The tutorial is split into four sections:
- Part 1: What Is Metamodeling and Code Generation All About
Wolfgang Ecker, Infineon; Michael Velten, Infineon
(00:00) - Part 2: Well Known Metamodels in EDA and Design: UML/SysML
Rainer Findenig, Intel; Wolfgang Ecker, Infineon
(44:23) - Part 3: Well Known Metamodels in EDA and Design: IP-XACT
Wolfgang Mueller, Heinz Nixdorf Institute; Daniel Müller-Gritschneder, Technical University of Munich
(57:39) - Part 4: Self-Paced Tutorial: VHDL Code Generation from IP-XACT Using the Eclipse Modeling Framework (EMF)
Daniel Müller-Gritschneder, Technische Universität München
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