Accellera at DAC and Beyond

By Gabe Moretti
June 30, 2015

Accellera has a strong tradition at DAC presenting its Tuesday morning breakfast.  This year was not an exception.  The food was good and abundant, offering a variety of choices for both vegetarians and meat lovers alike.  The program consisted of the presentation of the Leadership Award and a panel discussion on “Design and Verification Standards in the Era of IoT.”

The Leadership Award

The award recognizes the vision, leadership, and contribution to standards development, governance and promotional activities of the organization.  The recipient of this year’s award is Dr. Bill Read.  Dr. Read has been a member of Accellera’s Board of Directors since 1998. He currently serves on the SRC/GRC Executive Technical Advisory Board. Dr. Read received his BSE, MSE and PhD degrees in Electrical Engineering from the University of Texas at Austin.

Dr. Read has been involved in the technology industry for more than 30 years, beginning with Bell Labs in 1980.  As one of the longest serving members of Accellera’s Board of Directors, Dr. Read has been instrumental in bringing together some of the industry’s best technologists and engineers to collaborate to develop standards that have been widely accepted around the world.  His contributions from the user perspective have helped initiate standardization of IP Tagging and Verilog-AMS, bring low power standards under one umbrella, and develop and implement Universal Verification Methodology (UVM), which is proceeding to IEEE for standardization under the IEEE P1800.2 working group.

“Bill has been an integral part of Accellera’s history,” stated Shishpal Rawat, Accellera Systems Initiative chair.  “Over the years he has been an active supporter of EDA and IP standards development activities, bringing together industry leaders to influence their development within the industry.  His leadership within our organization is evident in his management style and the ease with which he helped transition Accellera’s policies and procedures during our mergers. He is well-deserving of this award.”

“I am honored to receive this award from my colleagues,” stated Dr. Read, Distinguished Member of Technical Staff at Freescale Semiconductor.  “Working with Accellera has allowed me to collaborate with key leaders in EDA and IP standards development.  We have made significant contributions over the years, and I look forward to continuing to work with Accellera members in standards innovation.”

The Panel Discussion

The era of Internet of Things (IoT) will usher increased use of communication and other protocols for rapid development and interconnect of new devices. These projects will be run on shrinking timelines with more globalized teams, increasing the need for design and verification standards. I2C, MIPI, WiFi and other protocols are already implemented using SystemC, SystemVerilog, UPF, UVM and other standards originated by Accellera and globalized in the IEEE. By working more closely together, the protocol working groups and the design and verification working groups can provide key technology to accelerate development in the era of IoT.

The panel was moderated by John Blyler, Editorial Director, Embedded IoT Systems.  John has been writing in the EDA industry for years and has moderated a number of panels.  The panelists were: Lu Dai, Director of Engineering at Qualcomm, Wael William Diab, Senior Director Strategy Marketing, Industry Development & Standardization at Huawei, and Chris Rowen, Chief Technology Officer of the IP Group at Cadence.

Of course there are many standards first developed by Accellera and later standardized by the IEEE, used by engineers in developing all types of products, including IoT ones, today.  But Diab said, “As IoT becomes more pervasive, we have to solve the standards issue. There won’t be one single standard for all IoT applications.”  Communication standards, both for wired and wireless communications will be required, at the physical as well as the logical levels.  Thus more than one standard will be needed.

To develop a standard is not simple.  The team must not only use technological tools and predict future uses, but must also respect existing implementations.  Dai observed, “There are a lot of standards around the world for 4G LTE for example”, estimating that there are 30 to 40 different 4G LTE standards. “We at Qualcomm have to make a chip to go across all of these standards.”   Rowen added, “The lack of understanding between analog and digital may become an issue in the IoT.  The concept of ‘system’ is still too parochial, we need to address not only the electrical but also the mechanical analog information in the transition to digital.”

System Level Power Workshop

Low power remains a hot topic for designers, verification engineers, IP developers and tool providers. Besides agreeing on the definition of system level, creation of power models and their suitability at different levels of abstraction for appropriate analysis remains a challenge.  Today low power is no longer a special application domain.  Power conservation is now a requirement of every system design, whether wireless or wired.

With this in mind, a System Level Power workshop was held at DAC. The workshop was co-organized and sponsored by the IEEE Design Automation Standards Committee (DASC), Si2 and Accellera.  The workshop was held on Tuesday afternoon and was well attended.   After a presentation from users with experiences managing power ranging from Microsoft to TSMC, existing standards were discussed.

Stan Krolikoski, Chair of the DASC LP Coordination Committee, presented the view from the IEEE which already has three standards dealing with Low Power issues.  They are: IEEE 1801 (initially developed by Accellera), IEEE 2415, and IEEE 2416.  Jerry Frenkil, Director of Low Power at Si2 described the methodology followed by the Si2 Low Power Coalition.  A good discussion followed the presentations but it is clear that much work remains in this area. All of the presentations from the System Power workshop can be downloaded from here.

DVCon Conferences in India and Europe

Following the success of last year’s inaugural conferences in the two locations, Accellera is hard at work to insure that both conferences will provide optimum service to attendees, presenters, and exhibitors alike.

DVCon India will be held in Bangalore on September 10 and 11.  Calls for both papers and tutorials went out some time ago and they will close on July 15.  For more information go to dvcon-india.org.

DVCon Europe will be held in Munich Germany on November 11 and 12.  For more information go to dvcon-europe.org.

These two conferences acknowledge the demand worldwide for papers that describe users’ experiences with standards, tools, and methods.  Past papers have documented the creativity of designers as well as the needs for further development of tools and standards.  Since travel restrictions have increased due to cost, it is only natural that Accellera would bring the extremely popular DVCon USA experience to other continents.